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Hammad M. Cheema, Reza Mahmoudi, Arthur van Roermund (Beteiligte)

60-GHz CMOS Phase-Locked Loops


2010. 2014. viii, 197 S. 12 Tabellen. 235 mm
Verlag/Jahr: SPRINGER NETHERLANDS; SPRINGER 2014
ISBN: 9400790392 (9400790392)
Neue ISBN: 978-9400790391 (9789400790391)

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The promising high data rate wireless applications at millimeter wave frequencies in general and 60 GHz in particular have gained much attention in recent years. This book focuses on phase-locked loops for 60 GHz wireless transceivers.
Abstract This chapter lays the foundation for the work presented in latter chapters. The potential of 60 GHz frequency bands for high data rate wireless transfer is discussed and promising applications are enlisted. Furthermore, the challenges related to 60 GHz IC design are presented and the chapter concludes with an outline of the book. Keywords Wireless communication 60 GHz Millimeter wave integrated circuit design Phase-locked loop CMOS Communication technology has revolutionized our way of living over the last century. Since Marconi´s transatlantic wireless experiment in 1901, there has been tremendous growth in wireless communication evolving from spark-gap telegraphy to today´s mobile phones equipped with Internet access and multimedia capabilities. The omnipresence of wireless communication can be observed in widespread use of cellular telephony, short-range communication through wireless local area networks and personal area networks, wireless sensors and many others. The frequency spectrum from 1 to 6 GHz accommodates the vast majority of current wireless standards and applications. Coupled with the availability of low cost radio frequency (RF) components and mature integrated circuit (IC) techn- ogies, rapid expansion and implementation of these systems is witnessed. The downside of this expansion is the resulting scarcity of available bandwidth and allowable transmit powers. In addition, stringent limitations on spectrum and energy emissions have been enforced by regulatory bodies to avoid interference between different wireless systems.
1 Introduction. 2 Synthesizer system architecture; 2.1 IEEE 802.15.3c channelization; 2.2 60 GHz frequency conversion techniques; 2.3 Proposed PLL architecture - flexible, reusable, multi-frequency; 2.4 System analysis and design; 2.5 System simulations; 2.6 Target specifications; 2.7 Summary. 3 Layout and measurements at mm-wave frequencies; 3.1 Layout problems and solutions; 3.2 Measurement setups; 3.3 Conclusions.- 4 Design of high frequency components; 4.1 Prescaler; 4.2 Voltage Controlled Oscillator; 4.3 Synthesizer front-ends; 4.4 Conclusions.- 5 Design of low frequency components; 5.1 Feedback division; 5.2 Phase-frequency detector, charge-pump and loop filter; 5.3 Conclusions.- 6 Synthesizer integration; 6.1 Synthesizer for 60 GHz sliding-IF frequency conversion; 6.2 Synthesizer with down-conversion mixer in feedback loop; 6.3 Dual-mode synthesizer; 6.4 Conclusions.- 7 Conclusions.- Appendix. References.